Non-DLL Clock Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The non-DLL clock mode is automatically selected by the controller when the clock frequency is 25 MHz or less. The frequency is controlled by the IOU_SLCR.SD_CONFIG_REG1 [SDx_BASECLK] and SDIO.reg_clockcontrol [clkctrl_sdclkfreqsel] bit fields as shown in Table: Non-DLL Mode Frequencies.

Table 26-3:      Non-DLL Mode Frequencies

[SDx_BASECLK] (MHz)

[clkctrl_sdclkfreqsel](1)

Actual BASECLK Divider Value(2)

SD Output Frequency(3) (MHz)

200

4

8

25

5

10

20

6

12

16.67

100

2

4

25

3

6

16.67

4

8

12.5

5

10

10

50

1

2

25

2

4

12.5

3

6

8.3

4

8

6.26

5

10

5

25

1

2

12.5

2

4

6.125

3

6

4.12

4

8

3.12

5

10

2.5

Notes:

1.The [clkctrl_sdclkfreqsel] bit field must not be set to 0.

2.See the description of SDIO.reg_clockcontrol register in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].

3.Maximum clock frequencies are specified in the Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2] data sheet.