Non-DMA Read Transfer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The buffer read ready interrupt is asserted whenever a block of data is ready in one of the FIFOs. On receiving the buffer read ready interrupt, the Arm processor acts as a master and starts reading the data through the buffer data port register (FIFO_1). The receiver starts reading the data from the SD bus only when a FIFO is empty and can receive a block of data. When both the FIFOs are full, the host controller stops the data coming from the card through a read wait mechanism (if the card supports a read wait mechanism) or by stopping the clock.