Non-DMA Write Transfer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

On receiving the buffer write ready interrupt, the Arm processor acts as a master and starts transferring the data through the buffer data port register (FIFO_1). The transmitter starts sending the data in the SD bus when a block of data is ready in FIFO_1. While transmitting the data in the SD bus, the buffer write ready interrupt is sent to the Arm processor for the second block of data. The Arm processor acts as a master and starts sending the second block of data through the buffer data port register to FIFO_2. The buffer write ready interrupt is only asserted when a FIFO is empty to receive a block of data.

12.Write a 1 to the buffer write ready in the normal interrupt status register to clear this bit.

13.Write the block data (in accordance with the number of bytes specified in step 1) to the buffer data port register.

14.Repeat until all the blocks are sent and then go to step 19.