Non-FIFO Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

These interrupt status bits are in the Chnl_int_sts register.

TOUT: Receiver Timeout Error interrupt status. This event is triggered whenever the receiver timeout counter has expired due to a long idle condition.

PARITY: Receiver Parity Error interrupt status. This event is triggered whenever the received parity bit does not match the expected value.

FRAMING: Receiver Framing Error interrupt status. This event is triggered whenever the receiver fails to detect a valid stop bit. See Receiver Data Capture.

DMS: indicates a change of logic level on the DCD, DSR, RI or CTS modem flow control signals. This includes High-to-Low and Low-to-High logic transitions on any of these signals.