Operation

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU is responsible for handling the primary pre-boot tasks and management of the PS hardware for reliable power up/power down of system resources and system error management. Optionally, the PMU can run the Xilinx Software Test Library. The power-on-reset (POR) initiates the PMU operation which directly or indirectly releases resets to any other blocks that are expected to be powered up.

In the PS, the APU MPCore and Cortex-R5F are classified as power masters. Power masters in the system are entities that can trigger the power down or power up of all islands including themselves.

GPU pixel processors, USB, PL, and memory blocks are classified as power slaves as their power management is triggered by one of the power masters. The power masters can also be slaves because their islands can be individually powered down.

When the processors in the PS are powered down, the PMU is the sole entity in the PS that can capture a request to power up the required system and wake up the target processor.

PMU GPIs can be used as inputs for external wake signals. The ULPI and RGMII are potentially used for wakes on USB 2.0 and Ethernet, respectively. PMU GPOs are used for sending signals to power supplies and communicating errors. For a detailed description of PMU GPIs and GPOs, see PMU GPIs and GPOs.