Output Mode

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In output mode, the pin values are driven by the corresponding register location. The direction control must be set to a 1 and the output enable set to a 1 for the output to be passed through the pad driven by MIO. The direction control and output enable can be controlled separately. The direction control can be used to disable input values being passed to the registers or APB write bus values being applied to input registers. The output enable can be used separately to control whether an output value is passed or not passed to the pin. The actual I/O pad direction control (gpio.OEN_{0:5}) is the logical combination of both these signals, the output enable value is masked when the direction mode is set to input.

In the output mode, when the output enable is active, the output pin value can be read from either the APB read only location or the APB read/write location. When the output enable is inactive, the pin is an input pin, and the value is available at the read only location. The register value that drives the inactive 3-state buffer can be read from the read/write location. The GPIO output and OEN signals are asserted and de-asserted asynchronously to all PL clocks.