Output Multiplexer

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The output multiplexer example in This Figure shows a single bit cell of an output multiplexer. The l3_output_* signal name is used to denote any of the range of low-speed peripherals, where the ordering is not significant. To illustrate the general multiplexing structure, other interfaces are identified without specifying a particular signal. Interfaces of similar speed can be swapped at each multiplexer level. For instance, the fast trace-port interface can be used where neither the ULPI nor RGMII PHY interfaces are used.

This Figure shows the default multiplexer structure for the output and enable multiplexer. For most pins, only one of the high-speed interfaces (RGMII or ULPI or trace) is present. Similarly, for many signals generated or consumed by peripherals, there is no corresponding 3-state enable under the implemented protocol for its external interface. For example, because RGMII does not use 3-state enables, the diagram includes them to illustrate the concept of the output enable shadowing the output signal.

Figure 28-2:      MIO Multiplexing Stages and 3-State Output Control

X-Ref Target - Figure 28-2

X18979-mux-three-state-data-output.jpg