Overview of the Blocks Function

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The MIO module can be described as a wide multiplexer/de-multiplexer, routing a number of different peripheral interfaces to a limited number of external pins under software configuration. A number of different interfaces are routed to and from the pins by the MIO, with varying timing requirements. Therefore, a priority structure based on maximum toggle rates must be implemented to place high-speed signal interfaces (such as gigabit Ethernet RGMII or USB ULPI) closer to the pin in the multiplexer tree structure.

Control of the functionality associated with each pin is through the MIO section of the IOU_SLCR system-level control registers. Output control signals are generated from these register settings. These signals are used either directly as multiplexer selects or indirectly through multiplexer select remapping functions. There are multiple port mapping options available for peripherals (e.g., 12 for CAN and I2C) where the interface to the peripheral can be constructed using any of the following.

Mapping of ports from a single group.

Mapping of ports from different groups.

A mix of PS pins and PL pins through the EMIO interface.