PCIe Bus Interface Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

As an Endpoint, the controller supports, legacy, MSI (multi-vector up to four) and MSI-X (up to four vectors) interrupt generation. These interrupts (when enabled) are generated by DMA transactions due to the completion of a DMA transfer or due to an error event. The mask for these events are enabled in the AXIPCIE_DMA*.DMA_CHANNEL_PCIE_INTERRUPT_CONTROL register. A coalesce count option is also provided for DMA completion events so that the frequency of interrupts can be controlled.

A software controlled interrupt is provided (per DMA channel) and can be asserted without enabling the DMA channel. Four scratchpad registers (per DMA channel) are also provided. These can be asserted by writing to the AXIPCIE_DMA*.DMA_CHANNEL_PCIE_INTERRUPT_ASSERT [pcie_software_interrupt] register. All interrupts require enabling of the AXIPCIE_DMA*.DMA_CHANNEL_PCIE_INTERRUPT_CONTROL[interrupt_mask] bit.

When in Endpoint mode, the bridge optionally generates interrupts when cfg_pcie_int_axi_pcie_n = 0. When MSI-X is enabled, the bridge implements an MSI-X table and PBA at fixed offset with regards to cfg_dma_reg_bar. Each DMA channel in the bridge uses one MSI-X vector for interrupts (for example, ith MSI-X table entry is used for ith DMA channel interrupt generation. Any miscellaneous interrupt uses the MSI-X table's 0th entry to generate MSI-X interrupt upstream.

Note:   As an Endpoint, when legacy interrupts are used, only INTA is supported.

 

IMPORTANT:   As a Root Port, if an Endpoint sends non-compliant MSI TLP, it will be dropped. It is required for the first byte-enable field in the MSI TLP to be equal to all ones.