PCIe to AXI Map

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Table: Ingress Transaction Map summarizes the PCIe-AXI transaction mapping.

Table 30-4:      Ingress Transaction Map

PCIe Transaction

AXI Transaction

Map Conditions

Memory read TLP

AXI read on AXI master port.

Translated address if ingress translation is hit.

If translation is not hit, and subtractive decode is enabled, forward to AXI without translation. Otherwise, unsupported request.

Memory write TLP

AXI write on AXI master port.

Translated address if ingress translation is hit. Otherwise, the same address (no translation) on subtractive decode.

Configuration TLP

Handled internally by the integrated block for PCIe.

Successful Cpl (CfgWr response)

AXI response OKAY.

 

Cpl with unsupported request (CfgWr response)

AXI response DEC_ERR.

 

Cpl with unsupported request (CfgRd response)

AXI response DEC_ERR if cfg_rd_ur_is_ur_ok1s_n = 1.

AXI response OKAY with data as all 1's when cfg_rd_ur_is_ur_ok1s_n = 0.

 

Cpl with completer abort

AXI response SLVERR.

 

Cpl with CRS

AXI response OKAY with data 0xFFFF0001 when CRS software visibility is enabled.

AXI response DECERR after 1s retry when CRS software visibility is not enabled.