PHY Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English
Table 32-7:      PHY Configuration

Task

Register

Bit Field

Register Offset

Bits

Value

To select port 0

SATA_AHCI_VENDOR.PCFG

[PAD]

0x00A4

5:0

5b'00010

PHY control OOB timing for the COMINIT parameters

SATA_AHCI_VENDOR.PP2C

ALL

0X00AC

31:0

‘h2818_4616

PHY control OOB timing for the COMWAKE parameters

SATA_AHCI_VENDOR.PP3C

ALL

0x00B0

31:0

‘h1308_1907

PHY control burst timing for the COM parameters

SATA_AHCI_VENDOR.PP4C

ALL

0x00B4

31:0

‘h064A_0815

PHY control retry Interval timing

SATA_AHCI_VENDOR.PP5C

[RCT]

0X00b8

31:20

‘hB00

Set host target speed

SATA_AHCI_PORTCNTRL.PxSCTL

[IPM], [SPD]

0x012C

11:4

'h33

Clear errors

SATA_AHCI_PORTCNTRL.PxSERR

ALL

0x0130

31:0

'hFFFF_FFFF