PHY Description

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PHY has four types of I/O buffers: address/command, data (8-bit blocks), clocking, and SSTL (configurable).

DDRPHYAC
The DDR SDRAM address/command PHY (DDRPHYAC) provides an address and command interface to the external SDRAM memories. A memory interface would typically contain a single address/command PHY.

DDRPHYDATX8
The DDR SDRAM data PHY (DDRPHYDATX8) provides data interface to one byte of an external SDRAM memory.

SSTL I/O library
The stub-series terminated logic (SSTL) I/O library includes process, voltage, and temperature (PVT)-compensated, on-die termination (ODT), and output impedance.