PHY Loopback

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The USB 3.0 host and device modes support PHY loopback. When the host/device with PHY connects to a tester during the polling state, the tester sends a TS2 ordered set with the loopback bit enabled. The host/device changes the link state from polling to loopback and asserts USB3_{0:1}_XHCI.TxDetRxLoopback.

Next, the tester sends TX data to the host/device, and the host/device PHY decodes the data and sends it back. There is no programming involved. When the tester finishes loopback testing and is ready to exit loopback mode, it performs a U2 or loopback (LFPS handshake) exit. See the USB 3.0 specification for more information.

This Figure shows a high-level diagram of the Zynq UltraScale+ MPSoC USB 3.0 block.

Figure 31-1:      Zynq UltraScale+ MPSoC USB 3.0 Block Diagram

X-Ref Target - Figure 31-1

X15497-usb-block.jpg

The controller can be visualized as software and embedded blocks. The embedded partition consists of USB 3.0 host/device and the associated PHY interfaces. Software drivers for host or device that connect the controller to the USB peripheral stack are available from either third-party or open source vendors.

The DC voltage bus (VBUS) can be controlled using PL signals only in non-OTG mode.

U2dsport_vbus_ctrl for USB 2.0

U3dsport_vbus_ctrl for USB 3.0

These signals are only used for non-OTG mode. There is no VBUS control port signal in USB 2.0 OTG mode with a ULPI interface. The VBUS control signal comes from the command.

Note:   Zynq UltraScale+ USB controller does not generate an external USB2.0 ULPI PHY RESET (ULPI_PHY_RESETB) signal. With Processor configuration wizard (PCW), signals can be generated with a reset logic. Please refer for more details in the Zynq UltraScale+ MPSoC Processing System Product Guide (PG201) for details.