PIO/DMA Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PIO/DMA controller implements the SDMA and ADMA2 engines as defined in the SD host controller specification and maintains the block transfer counts for PIO operation. It interacts with the registers set and starts the DMA engine when a command with data transfer is involved. The DMA controller interfaces to the host (AXI) master interface to generate memory transfers. The DMA controller also interfaces with the block buffer to store/fetch block data. The DMA controller implements a separate DMA for SDMA operation and separate DMA for the ADMA2 operation. In addition, it implements a host transaction generator that generates controls for the host master interface.

The DMA memory transactions will be routed to the CCI.