PJTAG Interface

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

An alternate option for communication with the Arm DAP is through the PJTAG signals. There are six PJTAG interfaces specified in the MIO. Using the MIO SLCR, you can select one of the PJTAG0-5 MIO interfaces to be the PJTAG interface. The PJTAG interface enters the JTAG security gate circuit, which routes the JTAG chain around the device.

To use the PJTAG interface, the following conditions must be met.

The JTAG security gate is disabled by writing to the correct register in the CSU.

The Arm DAP is not on the JTAG chain.

To prevent security holes, the PJTAG is multiplexed into the JTAG signaling before the security gate.

 

CAUTION!   The PJTAG interface can be disabled by the PS TAP controller when the Arm DAP controller is placed back on the JTAG chain using the JTAG_DAP_CFG register.

The JTAG interface signals are listed in Table: PJTAG I/O Interface.