PL Accelerator Block and FPD Interaction

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The DMA and the accelerator block are controlled by the APU through the M_AXI_HPMx_FPD interfaces. The DMA can access the PS-DDR through the S_AXI_HPCx_FPD or S_AXI_HPx_FPD interfaces. The difference is that the hardware assisted cache coherency using the HPC ports helps the software driver avoid costly cache flush/invalidate operations.