PL Accelerator Block and LPD Interaction

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

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2.4 English

In the PL accelerator block to LPD interaction, there is no path through the FPD (no PS-DDR access) to ensure functionality when FPD is powered down. The RPU controls the PL-based DMA and the accelerator block through the M_AXI_HPM0_LPD interface. The DMA can access the OCM through the S_AXI_LPD port.