PL Accelerator Block and LPD Interaction

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

In the PL accelerator block to LPD interaction, there is no path through the FPD (no PS-DDR access) to ensure functionality when FPD is powered down. The RPU controls the PL-based DMA and the accelerator block through the M_AXI_HPM0_LPD interface. The DMA can access the OCM through the S_AXI_LPD port.