PL Clearing

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The CSU contains the PCAP interface. The PCAP interface can be used to monitor the configuration memory's health in the PL. The PCAP CSU.pcap_prog [pcfg_prog_b] register bit can be used to erase the configuration memory in the PL and the CSU.pcap_status can be used to actively verify the contents have been erased. This provides a means of using PL configuration memory clearing as a tamper response.

A POR or soft reset, by default, clears the PL. There are applications where independence is needed between the PS and PL. To enable these applications, the ability to gate the reset/reprogramming of the PL is added through the PROG_GATE circuit. The PROG_GATE circuit can be controlled by the PMU_GLOBAL. PS_CNTRL.PROG_GATE and PROG_ENABLE bits as listed in Table: PROG_GATE Circuit Control

Table 12-10:      PROG_GATE Circuit Control

Prog_Enable

Prog_Gate

Description

0

0

Previous control maintained (This is the reset/power on state.  The PROG_GATE circuit powers on with the PS able to reset the PL).

0

1

pcfg_prog_b is blocked – PS reset does not reset the PL.

1

0

pcfg_prog_b is not blocked – PS reset does reset the PL.

1

1

Invalid condition.

After a successful configuration, SW can write to this register and configure the PROG_GATE circuit so that a soft reset to the PS does not clear the PL.

The behavior can be changed by programming any one of the three PROG_GATE[2:0] eFUSEs. These eFUSEs override the PROG_GATE circuit and force the PL to always be cleared upon a PS reset. The PROG_GATE[2:0] eFUSEs can be observed in the SEC_CTRL register in the eFUSE registers.