PL Configuration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The processor configuration access port (PCAP) is used to configure the programmable logic (PL) from the PS. The PCAP is the only interface used to configure the PL during normal operating conditions. The PCAP bus is 32 bits wide. During debug, the JTAG interface can be used to configure the PL. The PS is connected to the PCAP through the secure-stream switch. Bitstream data can be sent to the PL using either the CSU DMA or the AES path.