PL Configuration Reset

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

PL configuration reset is the default (but optional) effect of the PS system reset. If enabled, the PL configuration reset begins as de-assertion of the system reset (not immediately at the assertion of the system reset). The Zynq UltraScale+ device has an independent PS reset capability while the PL is still operating. To support the feature described in the PS Only Reset section, the PL configuration reset triggers can be blocked. If enabled, the PL configuration reset occurs optionally and does not begin until the de-assertion of the system resets. When the PL configuration is reset, the PL I/O pins are tri-stated and the PL configuration is cleared. The following table describes system reset input pins that can optionally trigger a PL configuration reset.

Table 38-4:      System Reset Input Pins That Can Reset the PL Configuration

Reset Pin Name

Description of Effect on PL Configuration

PS_POR_B

Power-on reset signal that resets the PS when asserted. Tri-stating of the PL I/O and clearing of PL configuration begins at the de-assertion of the PS_POR_B signal.

PS_SRST_B

System reset commonly used during debug to reset the PS. By default, but optional, tri-stating of the PL I/O and clearing of the PL configuration begins at the de-assertion of the PS_SRST_B signal.

PS_PROG_B

Direct PL configuration reset signal that tri-states PL I/O pins and clears the PL when asserted, except this input is blocked when PS_POR_B is asserted and blocked when the PS is setup for PS Only Reset

When there is a need to reset and stop operation of the whole Zynq UltraScale+ device, including the PL operation, Table: System Reset Input Pins That Can Reset the PL Configuration indicates that simply driving PS_POR_B Low is insufficient to reset and stop the PL operation. Instead, multiple options exist for resetting and stopping operation of the whole Zynq UltraScale+ device, including:

   Apply a High-Low-High pulse to PS_POR_B. Asserting PS_POR_B Low resets the PS, and the Low-to-High transition of the pulse assures the PL configuration is also reset.

   Assert PS_SRST_B and PS_PROG_B, but do not assert PS_POR_B, to reset the PS and reset the PL configuration.

   Assert PS_POR_B and use general output signals from the PMU to the PL to disable desired portions of the PL logic.