PL DMA using the HP and HPC Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The HP and HPC interfaces provide a high-performance datapath to the PS-DDR and the OCM memories. When using the HPC interface, requests from the PL to the PS-DDR go through the CCI which manages the APU MPCore cache coherent environment. These use-case topologies are shown in This Figure and are described in the following section.

Figure 35-6:      PL Coherent Masters

X-Ref Target - Figure 35-6

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