PL DMA via ACP

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The AXI ACP interface (S_AXI_ACP_FPD) provides a user IP topology similar to the high-performance S_AXI_HPx_FPD interfaces.

The ACP differs from the HP performance ports due to connectivity inside the PS. The ACP connects to the snoop control unit (SCU) that is also connected to the CPU L1 and the L2 cache.

This connectivity allows the ACP transactions to interact with the cache subsystems, potentially decreasing total latency for data to be consumed by a CPU. These cache-coherent operations can prevent the need to invalidate and flush cache lines. The ACP also has the lowest memory latency to memory of the PL interfaces. The connectivity of the ACP is similar to that of the CPUs.

The drawbacks from using the ACP include PL design complexity due to support of only two burst length transactions. Memory accesses through the ACP utilize the same interconnect paths as the APU, potentially decreasing CPU performance.

The ACP low-latency access allows opportunity for algorithm acceleration of medium granularity.