PL-PS Interface Specifics

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PL-PS interfaces are designed to provide a high-throughput datapath between the PL masters and PS memories, including the DDR and OCM memories. The main features of these interfaces are outlined in this section.

Support for AXI4. The conversion to AXI3 takes place in the PS.

Note:   Even though the channels within the PS can be AXI4 (for example, SMMU TBU to DDR memory controller) the transaction burst length is restricted to a maximum of 16, due to this conversion to AXI3 in the AXI FIFO interface (AFI).

32, 64, or 128-bit data-wide master interfaces that are independently programmed for read and write per port.

Efficient dynamic upsizing for all full-width AXI INCR commands.

Asynchronous clock frequency domain crossing for all AXI interfaces between the PL and PS. Two PL clocks per interface, one for read and one for write.

 

TIP:   Not all HP I/O ports have the exact same path to the various system resources especially the DDR memory control AXI port interface (XPI).

The S_AXI_HP1_FPD and S_AXI_HP2_FPD interfaces share exclusive access to an AXI Port Interface (XPI 4). This facilitates high throughput and relatively low-latency access from the PL directly to the DDR memory. S_AXI_HP0_FPD shares an XPI port on the memory controller with the DisplayPort master in the PL and S_AXI_HP3_FPD with the FPD DMA controller.

In video-based systems, S_AXI_HP0_FPD is typically used for video-type traffic and S_AXI_HP3_FPD is used for best-effort traffic.

Table 35-2:      AXI Interfaces and Associated Registers

Interface Name

Register Name

M_AXI_HPM0_FPD

FPD_SLCR

M_AXI_HPM1_FPD

FPD_SLCR

M_AXI_HPM0_LPD

LPD_SLCR

S_AXI_HPC0_FPD

AFIFM0

S_AXI_HPC1_FPD

AFIFM1

S_AXI_HP0_FPD

AFIFM2

S_AXI_HP1_FPD

AFIFM3

S_AXI_HP2_FPD

AFIFM4

S_AXI_HP3_FPD

AFIFM5

S_AXI_LPD

AFIFM6