PL SYSMON Register Access Arbitration

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PL SYSMON unit can be accessed using only one of the following ports.

DRP via APB slave connected to AXI and the PS.

DRP via PL (using the instantiated SYSMONE4 primitive).

I2C/PMBus connected to device pins.

JTAG PL TAP controller.

If the bitstream instantiates the SYSMONE4 primitive, then the PL design has control over the DRP interface to the PLSYSMON registers. The PS does not have access unless an alternative DRP to APB to AXI interface is established in the PL fabric and connected to a PS-PL AXI interface. The state of the native AXI interface to the PLSYSMON registers is reflected by the AMS.PL_SYSMON_CONTROL_STATUS [accessible] bit.

The PS should avoid attempts to access a PL SYSMON registers whenever a JTAG or I2C/PMBus transaction is accessing them. The APB interface assumes that it has dedicated access to the PL SYSMON registers. Simultaneous attempts to access the PL SYSMON via JTAG or I2C/PMBus can lead to unpredictable behavior of the PS. The JTAG and I2C/PMBus interfaces are available prior to PL configuration so appropriate caution and measures should be taken to avoid conflict if the PS also uses the APB interface while the device is in this state. Dedicated access to the PL SYSMON via the APB interface can be guaranteed following PL configuration with a design that does not instantiate the SYSMONE4 primitive. PL configuration disables the I2C/PMBus interface.

The JTAG interface can be disabled by generating a configuration image using the set_property BITSTREAM.GENERAL.JTAG_SYSMON DISABLE [current_design] option.

Figure 9-6:      Register Access Paths

X-Ref Target - Figure 9-6

X19415-register-paths.jpg