PL SYSMON Sensor Channels

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PL SYSMON sensors are controlled by the PLSYSMON register set. The 3-digit offset addresses in Table: PL SYSMON Sensor Channels are relative to the base address 0xFFA5_0C00.

Table 9-3:      PL SYSMON Sensor Channels

Sensor
Channel
Name

Description

Channel Number

Alarm No.

Register Address Offsets

Sequence Channel, Low-rate, and Average Registers

Input Mode and Long Acquisition Time Register

AMS Interrupt Registers

Input
Circuit

Alternate
Channel
Name

Measurement

Min/
Max

Alarm U/L

Temp_PL

SYSMON temperature.

0

0

000

080
090

140
150

0

~

ISR_0 [16]

Temp

PL_TEMP

Temp_PL_OT

Over temperature (OT).

~

~

~

~

14C
15C

~

~

ISR_1 [2]

Temp

~

VCCINT

PL internal voltage.

1

1

004

084
094

144
154

0

~

ISR_0 [17]

3V

SUPPLY1

VCCAUX

PL auxiliary voltage.

2

2

008

088
098

148
158

0

~

ISR_0 [18]

3V

SUPPLY2

VP_VN

Analog input pins.

3

3

00C

~

~

0

0

 

Uni 1V, or

Bi ±0.5V

VP/VN

VREFP

ADC positive V ref.

4

4

010

~

~

0

~

ISR_0 [20]

3V

~

VREFN

ADC negative V ref.

5

5

014

~

~

0

~

ISR_0 [21]

3V

~

VCCBRAM

PL block RAM voltage node.

3

3

018

08C
09C

160
170

0

~

ISR_0 [19]

3V

SUPPLY3

~

OR of alarm bits [22:16].

~

7

~

~

~

~

~

ISR_0 [23]

~

~

VCC_PSINTLP

LPD power supply.

13

~

034

0A0
0B0

164
174

0

~

Use PS SYSMON unit.

3V

SUPPLY4

VCC_PSINTFP

FPD power supply.

14

~

038

0A4
0B4

168
178

0

~

Use PS SYSMON unit.

3V

SUPPLY5

VCC_PSAUX

PS auxiliary voltage.

15

~

03C

0A8
0B8

16C
17C

0

~

Use PS SYSMON unit.

3V

SUPPLY6

VAUXP{0:15}
VAUXN{0:15}

Analog wires in PL fabric.(1)

16 - 31

~

040 to 07C

~

~

1

1

~

Uni 1V, or

Bi ±0.5V

~

VUser0

Analog wires in PL fabric.

32

8

200

280
2A0

180
1A0

2

~

ISR_0 [24]

3V or 6V

SUPPLY7

VUser1

Analog wires in PL fabric.

33

9

204

284
2A4

184
1A4

2

~

ISR_0 [25]

3V or 6V

SUPPLY8

VUser2

Analog wires in PL fabric.

34

10

208

288
2A8

188
1A8

2

~

ISR_0 [26]

3V or 6V

SUPPLY9

VUser3

Analog wires in PL fabric.

35

11

20C

28C
2AC

18C
1AC

2

~

ISR_0 [27]

3V or 6V

SUPPLY10

~

OR of alarm bits [29:16].

~

15

~

~

~

~

~

ISR_0 [31]

~

~

Notes:

1.The auxiliary channels can be enabled by writing 0001h to the SUPPLY2 (PL SYSMON) register prior to PL configuration. After PL configuration, the auxiliary channels can be connected to the PL analog wires using the SYSMONE4 instantiation.

2.Base addresses are used only while the PL Sysmon is not instantiated. For instantiation of base address refer to the Vivado block design.