PL to PS and PS to PL are the most common use cases of cross triggering in Zynq UltraScale+ MPSoCs. There are four trigger inputs on PL CTI, which can be configured to halt (EDBGRQ) any of the CPUs. Similarly, the four PL CTI trigger outputs can be triggered when a CPU is halted (DBGACK). The PL trigger inputs and outputs can be connected to ILA cores so that an ILA trigger can halt the CPUs and the ILA can be triggered to capture the signals it is monitoring when any of the CPUs are halted. For more information on setting up cross triggers to the FTM in the Vivado tools, see the "Cross Trigger Design" section in Vivado Design Suite: Embedded Processor Hardware Design (UG940) [Ref 24].