PLL Integer Divide Helper Data Table

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

For each unique value multiplier value, program the PLLs using registers in the CRL_APB and CRF_APB register sets (LPD and FPD). Each of the five PLLs have a set of integer programming parameters:

°{CRL, CRF}_APB.xPLL_CFG[CP]

°{CRL, CRF}_APB.xPLL_CFG[RES]

°{CRL, CRF}_APB.xPLL_CFG[LFHF]

°{CRL, CRF}_APB.xPLL_CFG[LOCK_DLY]

°{CRL, CRF}_APB.xPLL_CFG[LOCK_CNT]

Table: PLL Integer Feedback Divider Helper Data Values provides the PLL configuration register programming values when the PLL is in integer mode. The frequency of the VCO must stay within the range specified in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].

Table 37-1:      PLL Integer Feedback Divider Helper Data Values

FBDIV

CP

RES

LFHF

LOCK_DLY

LOCK_CNT

25

3

10

3

63

1000

26

3

10

3

63

1000

27

4

6

3

63

1000

28

4

6

3

63

1000

29

4

6

3

63

1000

30

4

6

3

63

1000

31

6

1

3

63

1000

32

6

1

3

63

1000

33

4

10

3

63

1000

34

5

6

3

63

1000

35

5

6

3

63

1000

36

5

6

3

63

1000

37

5

6

3

63

1000

38

5

6

3

63

975

39

3

12

3

63

950

40

3

12

3

63

925

41

3

12

3

63

900

42

3

12

3

63

875

43

3

12

3

63

850

44

3

12

3

63

850

45

3

12

3

63

825

46

3

12

3

63

800

47

3

12

3

63

775

48

3

12

3

63

775

49

3

12

3

63

750

50

3

12

3

63

750

51

3

2

3

63

725

52

3

2

3

63

700

53

3

2

3

63

700

54

3

2

3

63

675

55

3

2

3

63

675

56

3

2

3

63

650

57

3

2

3

63

650

58

3

2

3

63

625

59

3

2

3

63

625

60

3

2

3

63

625

61 to 82

3

2

3

63

600

83 to 102

4

2

3

63

600

103

5

2

3

63

600

104

5

2

3

63

600

105

5

2

3

63

600

106

5

2

3

63

600

107 to 125

3

4

3

63

600