PLL Lock Status

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Each of the four PS-GTR lanes contain its own PLL clock circuit. The input for each clock circuit is individually selected from one of several clock sources using the PCW. The PLL status can be read using the L{0:3}_PLL_STATUS_READ_1 [pll_lock_status_read] register bit 4. The PLL generates a wide number of frequencies. The required GTR clock frequencies for each protocol are listed in Table: Reference Clock per Protocol.

Note:   The PLL lock status bit is valid only after GTR reset (GTR reset is performed by a controller reset). After the lock bit is set, it stays set until another reset occurs (i.e., during normal operation, if the PLL lock is lost, the lock status bit will not update).