PLL Source Clocks

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The source clock for the PLL clock units is selected from one of five sources (see This Figure). All of these source clocks are inputs to each PLLs clock unit.

PS_REF_CLK (device pin, normal source).

ALT_REF_CLK (one of two MIO pins).

VIDEO_REF_CLK (one of two MIO pins).

AUX_REF_CLK (PL fabric source).

GTR_REF_CLK (multiplexer output from GTR serial unit).

The GTR_REF_CLK clock is rarely used but can be sourced from a PS GTR peripheral selected using the SIOU.CRX_CTRL [refclk_sel] bit field. The GTR clock specifications are listed in Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) [Ref 2].

0:  PCIe/USB

1: DisplayPort

2: SATA

3: SGMII

The PS_REF_CLK clock is always used for booting the system and is the default clock source for the system PLLs. After the system boots, the other reference clock sources can be selected to drive any of the PLL system clock units.

The PL clock throttle function is described in the Programmable Clock PL Throttle section.

Note:   Actively used PLL units must be put into bypass mode (xPLL_CTRL [BYPASS]) before reprogramming the clock frequency. After programming, wait for the PLL_STATUS [xPLL_LOCK] status bit to assert, then select the PLL output by disabling bypass.

Figure 37-2:      PLL Clock Unit Block DiagramNote:   Not all hardware features in this reference manual may be implemented in Xilinx design tools.

X-Ref Target - Figure 37-2

X19868-pll-clock-unit-block-diagram.jpg