PMU GPIs and GPOs

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU processor includes four local (only accessible by the PMU processor) GPI banks and four GPO banks. GPI0 and GPO0 are reserved for the dedicated PMU processor subsystem features (see PMU Processor), while GPI3 and GPO3 are reserved for communication with the PL. GPI1, GPI2, GPO1, and GPO2 are used for communication between the PS hardware features and the PMU.

The PMU’s general-purpose I/O features include miscellaneous wake, errors, and handshaking signals. The usage of the GPIs and GPOs can be summarized as follows with all signals being active-High unless otherwise specified.

GPI0 is used internally by the PMU processor. GPI0[31:0] shows the value of the fault-tolerance status register.

GPI1 monitors wake-up requests. Table: GPI1 Bit Descriptions describes the various GPI1 bit(s).

Table 6-6:      GPI1 Bit Descriptions

Bit(s)

Description

GPI1[3:0]

ACPU3-ACPU0 wake from APU GIC associated with ACPU3-ACPU0.

GPI1[5:4]

R5_1 and R5_0 wake from RPU GIC associated with R5_1 and R5_0.

GPI1[7:6]

USB1 and USB0 wake.

GPI1[8]

DAP full-power domain wake-up request.

GPI1[9]

DAP RPU wake-up request.

GPI1[15:10]

General purpose wake-up and event signals from MIO (see Table: PMU General Purpose MIO pins).

MIO[26] -> GPI1[10]
MIO[27] -> GPI1[11]
...
MIO[31] -> GPI1[15]

GPI1[16]

Full-power domain wake directed by the GIC proxy.

GPI1[19:17]

Reserved.

GPI1[23:20]

APU debug power-up request for ACPU3-ACPU0 APU MPCore processors 0, 1, 2, 3.

GPI1[27:24]

Reserved.

GPI1[28]

Error interrupt to PMU from error register 1.

GPI1[29]

Error interrupt to PMU from error register 2.

GPI1[30]

AXI AIB access error. A powered-down block is accessed through AXI.

GPI1[31]

APB AIB access error. A powered-down block is accessed through APB.

GPI2 monitors power control requests. Table: GPI2 Bit Descriptions describes the various GPI2 bit(s).

Table 6-7:      GPI2 Bit Descriptions

Bit(s)

Description

GPI2[3:0]

Power-down request from APU core {3:0}.

GPI2[5:4]

Power-down request from RPU core {1:0}.

GPI2[6]

Read the state of the pcfg_por_b input from PL, which signifies that PL is properly powered up.

GPI2[7]

Reserved.

GPI2[8]

Request to reset RPU core 0 by debug.

GPI2[9]

Request to reset RPU core 1 by debug.

GPI2[15:10]

Reserved.

GPI2[16]

Warm reset request for APU core 0.

GPI2[17]

Warm reset request for APU core 1.

GPI2[18]

Warm reset request for APU core 2.

GPI2[19]

Warm reset request for APU core 3.

GPI2[20]

Warm reset request for APU core 0 by debug logic.

GPI2[21]

Warm reset request for APU core 1 by debug logic.

GPI2[22]

Warm reset request for APU core 2 by debug logic.

GPI2[23]

Warm reset request for APU core 3 by debug logic.

GPI2[28:24]

Reserved.

GPI2[31:29]

Power rail removal alarms.

[31]: Asserts when VCC_PSINTFP is removed.

[30]: Asserts when VCC_PSINTLP is removed.

[29]: Asserts when VCC_PSAUX is removed.

GPI3 monitors the GPIs from the PL.

GPO0 is dedicated to the PMU features. Table: GPO0 Bit Descriptions describes the various GPO0 bit(s).

Table 6-8:      GPO0 Bit Descriptions

Bit(s)

Description

GPO0[0]

Used during debug to remap the 64-byte interrupt base vectors region to the RAM starting address (0xFFD0 0000).

0 = base vectors in ROM (default).

1 = base vectors in RAM.

GPO0[2:1]

Set PIT0 prescaler.

x0 = PIT0 is a 32-bit timer with no prescaler.

01 = External prescaler.

11 = PIT1 is prescaler to PIT0.

GPO0[4:3]

Set PIT1 prescaler.

x0 = PIT1 is a 32-bit timer with no prescaler.

x1 = External prescaler.

GPO0[6:5]

Set PIT2 prescaler.

x0 = PIT2 is a 32-bit timer with no prescaler.

01 = External prescaler.

11 = PIT3 is prescaler to PIT2.

GPO0[7]

Set PIT3 prescaler.

0 = PIT3 is a 32-bit timer with no prescaler.

1 = External prescaler.

GPO0[8]

Used to suppress the comparison of the PMU processor trace bus to not detect a trace bus mis-compare during fault injection.

GPO0[9]

Controls if the PMU processor SLEEP instruction cause a processor hardware reset during recovery from lock-step mode due to voting mode comparison.

GPO0[10]

Makes it possible to clear the value of the fault tolerance status register.

GPO0[11]

Makes it possible to reset the fault tolerance state machine.

GPO0[12]

Controls if fault tolerance state machine reset of the PMU processor is generated or not.

GPO0[15:13]

Used to inject failures in the triple-redundant PMU processor.

GPO0[23:16]

Used as magic word #2 to reduce the risk of accidental commands controlling TMR operation being issued.

GPO0[31:24]

Used as magic word #1 to reduce the risk of accidental commands controlling TMR operation being issued.

GPO1 is dedicated to the MIO for signaling and power-supply management. Table: GPO1 Bit Descriptions lists the GPO1 register bits.

Table 6-9:      GPO1 Bit Descriptions

Bit(s)

Description

GPO1[5:0]

These bits can drive up to six MIO outputs, their usage is described in Table: PMU General Purpose MIO pins.

GPO1[31: 6]

Not implemented.

GPO2 is dedicated to the PMU-generated requests and acknowledges. Table: GPO2 Bit Descriptions describes the various GPO2 bit(s).

Table 6-10:      GPO2 Bit Descriptions

Bit(s)

Description

GPO2[5:0]

Reserved.

GPO2[6]

Used to enable a subset of signals between PL and PS after the PMU has determined that the PL is properly powered up.

GPO2[7]

PS status output from PMU to a dedicated PS general purpose I/O pad.

GPO2[8]

Acknowledge to FP wake-up request from DAP.

GPO2[9]

Acknowledge to RPU wake-up request from DAP.

GPO2[31:10]

Not implemented.

GPO3 is dedicated to the GPOs to the PL.