PMU Global Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The global register set includes registers that are used as a means of communication between the PMU and other blocks to synchronize activities regarding power/system management and reset.

The PMU global register set is mapped at address FFD8 0000FFDB FFFF. The registers are summarized in Table: Global Registers. For a bit-level description, refer to the PMU_GLOBAL section in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].