The global register set includes registers that are used as a means of communication between the PMU and other blocks to synchronize activities regarding power/system management and reset.
The PMU global register set is mapped at address FFD8 0000—FFDB FFFF. The registers are summarized in Table: Global Registers. For a bit-level description, refer to the PMU_GLOBAL section in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].