PMU I/O Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU I/O registers include all the registers associated with the interrupts, GPI/GPO, and the programmable interval timers (PITs). The PMU_IOMODULE registers control the interrupt controller, GPI{0:3}, GPO{0-3}, and PIT0-PIT3. The PMU_GLOBAL registers enable the system processors to control interrupts and trigger PMU service requests.The PMU processor memory map is shown in Table: PMU I/O Registers and Local Memory.

Table 6-5:      PMU I/O Registers and Local Memory

Memory Address

Size

Slave Interface

Accessible

AXI Interconnect

0xFFD0_0000

32 KB

PMU ROM

PMU only

Local bus

0xFFD4_0000

128 B

PMU_IOMODULE register set

PMU only

Local bus

0xFFD5_0000

1024 B

PMU_LMB_BRAM

PMU only

Local bus

0xFFD6_0000

128 B

PMU_LOCAL register set

PMU only

Local bus

0xFFD8_0000

1024 B

PMU_GLOBAL register set

System via XPPU

System bus

0xFFDC_0000

128 KB

PMU RAM memory

System via XPPU

System bus