PMU Interconnect

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

PMU includes a 2 × 3 interconnect which supports two AXI masters, two APB slaves, and one AXI slave. One of the masters is the 32-bit AXI master from the triple-redundant processor and the other is the low-power domain main interconnect. This AXI master is a port on its register switch allowing any master in the system to access the PMU slaves.

The two APB slaves are the PMU RAM and PMU global register file. The AXI slave is on the port routed to the LPD switch and only allows the accesses that were originated by the PMU processor to be routed to the PS slaves outside the PMU.

The PMU processor AXI master can generate a coherent transaction by setting the coherent bit in the PMU global control register. The PMU AXI master (from the LPD interconnect) always generates transactions with AWCACHE and ARCACHE equal to 4'b0001 regardless of the coherency bit. This implies that PMU requests are treated as device transactions that can be buffered.

The PMU interconnect implements TrustZone security. All accesses that are generated by the PMU are secure and only secure accesses are allowed to be routed to the PMU. The PMU interconnect will generate an error on any non-secure access to the PMU.