PMU Interrupts

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

When the PMU processor receives an interrupt, it branches to the PMU ROM. The ROM code must check the pending interrupt register within the interrupt controller in the PMU I/O module and branch to the appropriate interrupt service routine in the ROM or RAM. The priority between the pending interrupts can be enforced by the PMU firmware, and if not present, the priority is managed by the ROM. Table: PMU Interrupts lists the PMU interrupts.

Table 6-11:      PMU Interrupts

Bit in Interrupt Pending Register

External Interrupt

Description

31

Secure lock-down request

Interrupt from CSU to initiate a secure lock down.

30

Reserved

29

Address error interrupt

Interrupt for address errors generated during accesses to PS SLCRs or PMU global registers.

28

Power-down request

Interrupt to signal a power-down request.

27

Power-up request

Interrupt to signal a power-up request.

26

Software reset request

Interrupt to signal a software-generated reset request.

25

Hardware block RST request

Interrupt for all hardware-generated block reset requests.

24

Isolate request

Interrupt to signal an isolation request.

23

ScanClear request

Interrupt to signal a scan clear request.

22-19

IPI3-IPI0

Interrupt associated with IPI slices 3-0 to PMU.

18

RTC alarm interrupt

Interrupt from RTC to signal the alarm.

17

RTC seconds interrupt

Interrupt from RTC triggered every second.

16

Correctable ECC error

Interrupt generated when an ECC error on the PMU RAM is corrected.

15

Reserved

14

GPI3

Interrupt generated when any input on GPI3 changes from 0 to 1.

13

GPI2

Interrupt generated when any input on GPI2 changes from 0 to 1.

12

GPI1

Interrupt generated when any input on GPI1 changes from 0 to 1.

11

GPI0

Interrupt generated when any input on GPI0 changes from 0 to 1.

10-7

Reserved

6-3

PIT3-PIT0

Programmable interval timer interrupts.

2-0

Reserved