PMU Processor

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU processor is a triple-redundant processor without caches. The processing system provides fault tolerance by applying redundancy on the PMU and error correction (ECC) on the RAM interface. The triple redundancy and ECC corrects single errors and generates an error on multiple errors that cannot be corrected. When an error occurs with one of the PMU processors, it might not always be possible for the processor in error to properly continue operation. Thus, at some point, the PMU might require a reset for proper TMR operation.

There is a provision to allow more complex power protocol management programs to be implemented as firmware or application programs in the PMU RAM.

Note:   PMU processor debug module is disabled by default on ES2 and higher versions.

Table: MicroBlaze Implementation Features lists the implementation features for the PMU processor.

Table 6-2:      MicroBlaze Implementation Features

Feature

Implementation

Pipeline

5-stage.

Interconnect standard

AXI

Endianness

Little endian.

Program counter width

32

Support for load/store exclusive

Enabled.

Fault tolerance

Enabled.

Hardware multiplier/divider/barrel shifter

Disabled/disabled/enabled.

Debug

Enabled. One of each type of break-point.

Fast interrupt

Disabled.