PMU Processor Interfaces

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU provides input/output signals that are grouped functionally into the following interfaces.

32-bit AXI master interface to the low-power domain (LPD) interconnect that allows the PMU to access other PS resources including the SLCR registers and the IPI block.

32-bit AXI slave interface from the LPD inbound switch to allow accesses to the PMU global registers and the PMU RAM by external processors.

PMU clock and reset signals.

Power control interface to all islands within the PS.

°L2, OCM, and TCM RAMs.

°APU_Cores [3:0].

°Dual-core Cortex-R5F® real-time processor.

°USB0 and USB1.

°GPU pixel-processor (PP) PP0 and PP1.

°Full-power and PL domain crossing bridges.

Wake interface from GPIO, RTC, APU GIC, RPU GIC, and USBs.

Interrupt interface.

Device reset control interface.

Memory BIST and BISR control interface.

Other miscellaneous interfaces including the power-supply monitor interface. Table: PMU General Purpose MIO pins lists the PMU general purpose MIO pins.

Error capture and propagation interfaces. Table: Error Interface Signals To and From the PL lists the error capture and propagation signals.

Table 6-3:      PMU General Purpose MIO pins

Register Bit Fields

Pins

Size

Direction

Clock

Clamp Value

Description

GPI1[15:10]

MIO [31:26]

6

Input

Async

6’b0

Inputs for external events that are available to the PMU using six MIO pins. The GPI1 register bits are listed in Table: GPI1 Bit Descriptions. These signals are defined by FSBL, SDK, development boards, or users.

GPO1[5:0]

MIO [37:32]

6

Output

pmu_clk

 

Output signals to control external power supplies and other board hardware using MIO pins. See Table: GPO1 Bit Descriptions for pin assignments.

GPO1[0]: used by the PMU ROM code for the FPD's VCC_PSINTFP.

GPO1[1]: used by the PMU ROM code for the PL's VCCINT.

GPO1[2:5]: user defined (including Xilinx reference boards and customer designs). Not used by the PMU ROM code.

Table 6-4:      Error Interface Signals To and From the PL

Signal Name

Size

Direction

Clock

Clamp Value

Description

pmu_pl_err

4

Input

Async

4’b0

Generic PL errors communicated to PS.

pmu_error_to_pl

47

Output

pmu_clk

 

PS error communicated to the PL and JTAG.