Much of the PMU functionality is provided by software executed by the PMU processor. The ROM memory contains instructions that provide default functionality. To extend or replace these features, or to provide new features, software can be downloaded into the PMU processor’s 128 KB RAM. The PMU includes a 128 KB RAM with 32-bit ECC that is used to hold data and code. The PMU RAM is accessible both by the PMU processor and the external masters through the PMU AXI slave interface.
IMPORTANT: Accesses by the external masters should be 32-bit wide and word-aligned.
The PMU RAM allows only word writes, words are 4 bytes. It does not allow byte writes. If less than 4 bytes have to be written, then the 4 bytes must be read first, modified, and the entire 4 bytes must be written back.
For an external master to access the PMU RAM through the APB interface, the PMU processor must be in sleep mode. A PMU RAM access from an external master while the PMU processor is not asleep can hang the system. If the PMU processor is not put in sleep mode, it performs an instruction fetch or load/store on every clock cycle, which means that the APB never gets to access the RAM. In this case, starvation of the APB interface occurs.
The following is the order of priority to access the PMU RAM.
1.PMU processor data load/store.
2.PMU processor instruction fetch.