The PMU block uses both power-on reset (POR) and the system reset (SRST) inputs that are controlled by the reset block. POR clears the state of the PMU completely. All islands and power domains are powered up and all the isolations are disabled. After a POR, the PMU executes both scan and BIST clear functions on the LP and FP domains. However, the SRST will only reset the PMU processor subsystem, the PMU interconnect, and a subset of local and global registers, leaving most local and global registers in the states they were prior to the reset. When the SRST triggers the reboot of the PMU, the power state is not cleared and the power state of the PS is preserved. However, after a power-on reset, the power state is cleared by specifically clearing all RAMs and flip-flops.