PMU System-level View

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PMU block is located within the low-power domain. This Figure shows the block diagram of the PMU. It includes the following subcomponents:

Dedicated, fault-tolerant triple-redundant processor.

ROM to hold PMU ROM code that includes the PMU startup sequence, routines to handle power-up or down requests, and interrupts.

128 KB RAM with ECC used for code and data.

PMU local registers accessible only by the PMU.

PMU global registers accessible by the PMU processor and also by other bus masters within the system. These include all power, isolation, and reset request registers. It also includes error capture registers and the system power state registers.

32-bit AXI slave interface to allow masters outside the PMU to access the PMU RAM and the global register file.

PMU interrupt controller manages the 23 interrupts to the PMU. Four are from the inter-processor interconnect (IPI).

GPI and GPO registers interface to the PMU, MIO, PL, and other resources within the PS for signaling to and from the PMU.

°Six outputs and six inputs.

°32 GPO outputs to the PL from the PMU and 32 GPI inputs from the PL to the PMU.

°47 system errors to the PMU.

°CSU error code.

°32 memory built-in self test (MBIST) status signals and 32 MBIST completion signals.

°Three direct reset control signals.

°Four AIB status signals and four AIB control signals.

°11 logic clear status signals.

°DDR retention control.

°Three programmable settings to the CSU for the PL.

PMU MDM controller accessible using the PS TAP controller via the PSJTAG interface.

Figure 6-2:      PMU System Diagram

X-Ref Target - Figure 6-2

X15307-pmu-block.jpg