PMU User Firmware Controls

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Registers are used to control and set the status of the MBIST memory controllers via the PMU global register set. This register set can be protected by a 64 KB aperture of the Xilinx peripheral protection unit (XPPU). There are five control and status registers:

MBIST_RST controls the reset signal (rw)

MBIST_PG_EN controls the PG_EN signal (rw)

MBIST_SETUP controls the SETUP signal (rw)

MBIST_DONE indicates when the test is completed (ro)

MBIST_GOOD indicates the results of the test (ro)

To initiate an MBIST operation, set the bit in all three trigger registers: MBIST_RST, MBIST_PG_EN, and MBIST_SETUP. When the operation is finished, the software clears the associated bits in all three trigger registers. The MBIST_DONE bit goes High when the operation is finished. MBIST_GOOD provides the status of the operation: 0 (failure) or 1 (success). MBIST_DONE and MBIST_GOOD are read-only registers and cleared by the hardware when the trigger registers are cleared.

Table: MBIST Control Register Bit Fields lists the system elements that are tested by the MBIST and the bit assignments for the control and status registers.

Table 39-15:      MBIST Control Register Bit Fields

Bit   

Bit Field         

System Element

0:1

CAN{0,1}          

CAN {0,1} controller

2:5

GEM{0:3}          

GEM {0:3} controller

6

IOU               

IOP peripherals

7

RPU               

RPU cores

8

RPU_TIEOFF_WRAPPER

LPD less RPU

9:10

USB{0,1}          

USB controller {0, 1}

11

AFI_LPD           

S_AXI_LPD interface with FIFO memory

12

OCM               

OCM memory

13

PSS_CORE_TOP      

PS top core (includes XPPU and APM)

14

FPD

FPD(1)

15

AFI_0             

S_AXI_HPC0_FPD interface with FIFO memory

16

AFI_1             

S_AXI_HPC1_FPD interface with FIFO memory

17:20

AFI_{2:5}         

S_AXI_HP{0:3}_FPD interface with FIFO memory

21

APU               

APU MPCore

22:25

ACPU_{0:3}        

APU core {0:3}

26

DDR               

DDR controller

27

GPU               

GPU controller

28

M400_0            

GPU pixel processor 0

29

M400_1            

GPU pixel processor 1

30

SIOU              

High-speed serial I/O

31

PCIE              

PCIe controller

1.This bit is used to cover the rest of the memories in the FPD such as SMMU, debug, GDMA, and so on.