POR Reset Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The first stage is used to ensure that all the power rails are powered (up). The external PS_POR_B signal is taken from the IOB and passed through an AND gate with a signal from the power-on reset block. A glitch filter is used to ensure that the power is stable for 32 PS_REF_CLK cycles cycles. The sampling value from the boot mode pins are replicated three times and a voter circuitry is used to select the appropriate boot mode sample value. After releasing power-on reset (POR), the eFUSE is cached and scan clear starts up. The reset controller in the LPD holds full control of the system until the LPD reset sequence is completed. Post LPD reset sequence, the reset controller gives control to the PMU. See This Figure for the flow.

The system reset is deasserted once the reset logic hands off control to the PMU and is asserted back when an event, such as a debug system reset, occurs that needs to assert system reset.

Figure 38-2:      Reset Flow Performed by Reset Controller and PMU

X-Ref Target - Figure 38-2

X15257-reset-flow.jpg