PREAMBLE Field

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

DPDMA checks the validity of the descriptor by comparing the preamble with a predefined preamble value (0xA5). If there is an error in the preamble, the DPDMA goes to an invalid location to read the descriptor. This should result in a preamble mismatch. The DPDMA generates an interrupt to indicate this error.

Table 33-8:      DPDMA Descriptor Fields

Word Number

Field Name

Size (Bytes)

Bits

Description

0

control

4

[7:0]

Descriptor (8).

[8]

Enable completion interrupt (1).

[9]

Enable descriptor update (1).

[10]

Ignore done (1).

[11]

AXI burst type INCR or FIXED (1).

[15:12]

AXCACHE (4).

[17:16]

AXPROT bits (2).

[18]

Mode = descriptor mode.

0 = contiguous 1 = fragmented

[19]

Last descriptor (1).

[20]

Enable CRC (1).

[21]

Last descriptor of frame (1).

[31:22]

Reserved (3)

1

DSCR_ID

4

[15:0]

Descriptor ID (16)

[31:16]

Reserved(16)

2

XFER_SIZE

4

[31:0]

Indicates transfer size in both modes (in bytes) (32).

3

LINE_SIZE_STRIDE

4

[17:0]

Horizontal resolution (line size) (18).

[31:18]

Stride (14).

4

Timestamp LSB

4

[31:0]

If enabled, the DPDMA stores the LSB of the timestamp here (32).

5

Timestamp MSB

4

[9:0]

If enabled, the DPDMA stores the MSB of the timestamp here (10).

[30:10]

Reserved (21).

[31]

Status/done (1).

6

ADDR_EXT

4

[15:0]

Next descriptor extension (16).

[31:16]

SRC address extension (16).

7

NEXT_DESR

4

[31:0]

Address of the next descriptor (32).

8

SRC_ADDR

4

[31:0]

Source address (32).

9

ADDR_EXT_23

4

[15:0]

Address extension for SRC Addr2 (16).

[31:16]

Address extension for SRC Addr3 (16).

10

ADDR_EXT_45

4

[15:0]

Address extension for SRC Addr4 (16).

[31:16]

Address extension for SRC Addr5 (16).

11

SRC_ADDR2

4

[31:0]

Source address of 2nd page (32).

12

SRC_ADDR3

4

[31:0]

Source address of 3rd page (32).

13

SRC_ADDR4

4

[31:0]

Source address of 4th page (32).

14

SRC_ADDR5

4

[31:0]

Source address of 5th page (32).

15

CRC

4

[31:0]

Reserved (32).