PS I/O Peripherals Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The I/O peripheral registers are accessed through the 32-bit APB bus. The base addresses for both the low-power domain and the and full-power domain peripherals are listed in Table: I/O Peripherals Register Map (LPD) and Table: I/O Peripheral Register Map (FPD).

Table 10-6:      I/O Peripherals Register Map (LPD)

Base Address

Description

0xFF00_0000, 0xFF01_0000

UART0, UART1

0xFF02_0000, xFF03_0000

I2C0, I2C1

0xFF04_0000, 0xFF05_0000

SPI0, SPI1

0xFF06_0000, 0xFF07_0000

CAN0, CAN1

0xFF0A_0000

GPIO

0xFF0B_0000, 0xFF0C_0000,
0xFF0D_0000,
 0xFF0E_0000

GEM0, GEM1, GEM2, GEM3

0xFF0F_0000

QSPI

0xFF10_0000

NAND(1)(2)

0xFF16_0000, 0xFF17_0000

SD0, SD1

0xFF99_0000

IPI message buffer memory; see Table: IPI Channel and Message Buffer Default Associations.

0xFF9D_0000, 0xFF9E_0000

USB0, USB1

0xFFA5_0000, 0xFFA5_0800,
0xFFA5_0C00
(3)

System monitor register sets (AMS, PSSYSMON, PLSYSMON)

0xFFCB_0000

   CSU_SWDT, system watchdog timer (csu_pmu_wdt).

Notes:

1.NAND cannot be accessed through AXI as a linear mode peripheral.

2.AXI address cannot be directly translated to NAND memory address.

3.The default address for the PL SYSMON register set is 0xFFA5_0C00, but can be changed by instantiating the SYSMONE4 LogiCORE and mapping it to an M_AXI_HPMx_FPD or M_AXI_HPM0_LPD interface to the PL.

 

Table 10-7:      I/O Peripheral Register Map (FPD)

Base Address

Description

0xFD0C_0000

SATA registers (HBA, vendor, port-0/1 control)

0xFD0E_0000

AXI PCIe bridge

0xFD0E_0800

AXI PCIe ingress {0:7}

0xFD0E_0C00

AXI PCIe egress {0:7}

0xFD0F_0000

AXI PCIe DMA {0:7}

0xFD3D_0000

SIOU slave access ports

0xFD40_0000

PS GTR transceivers

0xFD48_0000

PCIe attributes

0xFD4A_0000

DisplayPort controller

0xFD4B_0000

GPU

0xFD4C_0000

DisplayPort DMA