PS-PL Voltage Level Shifters

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS communicates with the PL using voltage level shifters. All of the signals (input and output) and interfaces between the PS and PL traverse a voltage boundary and are routed through voltage-level shifters. Some of the voltage-level shifter enables are controlled by the PL power state including the signals for the PL, the EMIO JTAGs, the PCAP interface, and other modules. The PL is treated as a separate power domain (PLPD). The AXI interfaces are isolated using isolation blocks. To enable an PS-PL AXI interface, the PS-PL isolation must be disabled by making a PMU service request using the PMU_GLOBAL[REQ_PWRUP_INT_EN] bit.