PS SYSMON Sensor Channels

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS SYSMON sensors are controlled by the PSSYSMON register set. The 3-digit offset addresses in Table: PS SYSMON Sensor Channels are relative to the base address 0xFFA5_0800.

Table 9-2:      PS SYSMON Sensor Channels

Sensor
Channel
Name

Description

Channel Number

Alarm No.

Register Address Offsets

Sequence Channel, Low-rate, and Average Registers

AMS Interrupt Registers

PMU_Global
ERROR_STATUS_1

CSU
IOMODULE
ISR (1)

Input
Circuit

Alternate
Channel
Name

Measurement

Min/
Max

Alarm U/L

Temp_LPD

Temperature for RPU MPCore.

0

0

000

080
090

140
150

0

ISR_0 [0]

~

~

Temp

PS_TEMP1

Temp_LPD_OT

LPD over temperature (OT).

~

~

~

~

14C
15C

~

ISR_1 [1]

[4]

[20]

Temp

~

VCC_PSINTLP

LPD power supply.

1

1

004

084
094

144
154

0

ISR_0 [1]

[16]

[22]

3V

SUPPLY1

VCC_PSINTFP

FPD power supply.

2

2

008

088
098

148
158

0

ISR_0 [2]

[17]

[23]

3V

SUPPLY2

VCC_PSAUX

PS auxiliary voltage.

6

3

018

08C
09C

160
170

0

ISR_0 [3]

[18]

[24]

3V

SUPPLY3

VCCO_PSDDR

I/O bank 504: DDR PHY.

13

4

034

0A0
0B0

164
174

0

ISR_0 [4]

[19]

[25]

3V

SUPPLY4

VCCO_PSIO3

I/O bank 503: boot, config, JTAG, error, SRST, POR.

14

5

038

0A4
0B4

168
178

0

ISR_0 [5]

[20]

[27]

6V

SUPPLY5

VCCO_PSIO0

I/O Bank 500: MIO[0:25].

15

6

03C

0A8
0B8

16C
17C

0

ISR_0 [6]

[21]

[26]

6V

SUPPLY6

~

OR of PS alarms in bits [6:0].

~

7

~

~

~

~

ISR_0 [7]

~

~

~

~

VCCO_PSIO1

I/O bank 501: MIO[26:51].

32

8

200

280
2A0

180
1A0

2

ISR_0 [8]

[22]

[26]

6V

SUPPLY7

VCCO_PSIO2

I/O bank 502: MIO[52:77].

33

9

204

284
2A4

184
1A4

2

ISR_0 [9]

[23]

[26]

6V

SUPPLY8

PS_MGTRAVCC

GTR SerDes I/O.

34

10

208

288
2A8

188
1A8

2

ISR_0 [10]

~

[28]

3V

SUPPLY9, VMGTAVCC

PS_MGTRAVTT

GTR SerDes terminators.

35

11

20C

28C
2AC

18C
1AC

2

ISR_0 [11]

~

[28]

3V

SUPPLY10, VMGTAVTT

VCC_PSADC

PS SYSMON ADC circuitry.

36

12

210

290
2B0

190
1B0

2

ISR_0 [12]

~

~

3V

~

Temp_FPD

Temperature for APU MPCore.

37

13

214

294
2B4

194
1B4

2

ISR_0 [13]

~

~

Temp

T_REMOTE, Remote_Temp

Temp_FPD_OT

FPD over temperature (OT).

~

~

~

~

14C
15C

~

ISR_1 [0]

[5]

[21]

Temp

~

~

OR of PS alarms in bits [13:0].

~

15

~

~

~

~

ISR_0 [15]

~

~

~

~

Notes:

1.Three MIO banks are OR'd together for bit [26] and the two GTR supplies are OR'd together for bit [28].

2.The PSIO{1, 2} and the two GTR supplies are mapped to sensors channels {7:10} using the ANALOG_BUS register. This table shows the default mapping, see PS SYSMON Analog_Bus for more information.