PS System Registers

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

Registers not covered in the previous sections are listed in Table: PS System Register Map (LPD).

Table 10-8:      PS System Register Map (LPD)

Base Address

Description

0xFF30_0000

Inter-processor interrupts (IPI)

0xFF11_0000, 0xFF12_0000,
0xFF13_0000,
 0xFF14_0000

TTC0, TTC1, TTC2, TTC3

0xFF15_0000

LPD_SWDT, system watchdog timer (swdt0)

0xFF98_0000

XPPU (Xilinx peripheral protection unit)

0xFF9C_0000

XPPU_Sink

0xFF9B_0000

PL_LPD (S_AXI_LPD)

0xFFA0_0000

Arm for OCM interconnect

0xFFA1_0000

Arm for LPD to FPD interconnect

0xFFA6_0000

Real-time clock (RTC)

0xFFA7_0000

OCM_XMPU

0xFFA8_0000

LPD_DMA channels {0:7}

0xFFC8_0000

CSU_DMA

0xFFCA_0000

Configuration and security unit (CSU)

0xFFCD_0000

Battery-backed RAM (BBRAM) control and data

Table 10-9:      PS System Register Map (FPD)

Base Address

Description

0xFD00_0000

DDR_XMPU{0:5}

0xFD07_0000

DDR controller

0xFD08_0000

DDR PHY

0xFD09_0000

DDR QoS control

0xFD0B_0000

Arm for DDR

0xFD36_0000

HPC0 (S_AXI_HPC0_FPD)

0xFD37_0000

HPC1 (S_AXI_HPC1_FPD)

0xFD38_0000

HP0 (S_AXI_HP0_FPD)

0xFD39_0000

HP1 (S_AXI_HP1_FPD)

0xFD3A_0000

HP2 (S_AXI_HP2_FPD)

0xFD3B_0000

HP3 (S_AXI_HP3_FPD)

0xFD49_0000

Arm for CCI

0xFD4D_0000   

FPD_SWDT, system watchdog timer (swdt1)

0xFD50_0000

   FPD_DMA channels {0:7}

0xFD5D_0000

FPD_XMPU

0xFD4F_0000

XMPU_Sink (FPD)

0xFD5E_0000

CCI_REG register set wrapper: debug enables

0xFD5F_0000

SMMU_REG (interrupts, power, and unit control)

0xFD6E_0000   

CCI_GPV (CCI400, parameters)

0xFD70_0000

FPD_GPV (parameters)

0xFD80_0000

SMMU_GPV (SMMU500, parameters)

0xFE00_0000

   IOU_GPV (parameters)

0xFE10_0000

LPD_GPV (parameters)