PS TAP Controller

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS TAP controller can provide system access for itself, and the PL TAP and Arm DAP controllers. The PS TAP controller also provides basic PS-related functions. The device IDCODE is accessible using the PS TAP controller in most all device modes. Boundary-scan requires access to the PL TAP controller, i.e., the device must boot and the security gate must be disabled.

The PS TAP controller is designed to always be active in the system. To ensure security, the PS TAP controller has a limited command set. Before the PS boot is complete (CSU ROM code completes), the PS TAP can perform these instructions:

BYPASS

IDCODE

After the PS is booted, the PS TAP controller can be used to control the configuration of the JTAG chain (PL and DAP access). Once access to the PL is established, boundary-scan functions can be performed. The PL access and Arm DAP can only be connected to the JTAG chain if the security gate has been disabled by either the CSU ROM (non-secure boots) or by secure software running on the PS. With non-secure boots, the CSU ROM automatically links the PL TAP and Arm DAP to the JTAG.

The PS TAP controller state machine is reset to the test-logic-reset state by power-cycling the LPD.

The JTAG_TOGGLE_DETECT register is reset by PS_POR_B. The JTAG toggle detect is a security feature used to trigger a tamper response in the CSU when the JTAG signals are toggled.

The JTAG_DAP_CFG register is reset by a system reset.

The rest of the registers are reset when the PS TAP controller state machine is in the test-logic-reset state.

Assert a reset to the PS TAP controller through the software.