PS and PL Pins

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The MIO is fundamental to the I/O peripheral connections due to the limited number of MIO pins (This Figure). Software programs the routing of the I/O signals to the MIO pins. The I/O peripheral signals can also be routed to the PL (including PL device pins) through the EMIO interface. This is used to gain access to more device pins (PL pins) and to allow an I/O peripheral controller to interface to internal logic in the PL.

Figure 28-1:      MIO-EMIO Wiring Diagram

X-Ref Target - Figure 28-1

X15461-mio-emio-block.jpg