PS-only Reset Sequence

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS-only reset requirement is to reset the PS while the PL remains active. The PS-only reset can be triggered by a hardware error signal or a software register write. If the PS-only reset is due to an error signal, then the error must also be indicated to the PL.

The PS-only reset can be implemented as a subset of the system-reset. However, it needs to gracefully terminate the PS to PL AXI transactions before initiating a PS-only reset. A PS-only reset sequence can be implemented as follows.

1.Set pmu_global.PS_CNTRL[prog_gate] to 1 to block the PL from being reset when the PS is reset.

2.An error interrupt is asserted and the action requires a PS-only reset. This request is sent to the PMU as an interrupt.

3.To indicate to the PL, set the PMU error (PS-only reset).

4.Block the FPD to PL and the LPD to PL interfaces with the help of the AMBA isolation block (AIB).

5.If the AIB acknowledgment is not received, then the PMU should timeout and continue.

6.Block the PL to FPD and PL to LPD interfaces with the help of the AIB (in the PL design).

7.If the AIB acknowledgment is not received, then the PMU should timeout and continue.

8.Initiate a PS-only reset by writing to the PMU global reset request register.

9.Assert a PS-only reset by writing to the pmu_global.GLOBAL_RESET[ps_only_rst] bit. This bit is self clearing and causes a PS only reset.

10.Release all signals from being isolated between the PS and PL.