PS_SRST_B Reset Pin During Hardware Boot

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID
UG1085
Release Date
2022-09-15
Revision
2.3 English

The PS_SRST_B input pin is disabled after PS_POR_B is released and stays disabled during the first part of CSU ROM execution.

For non-secure boot, the PS_SRST_B input is enabled before loading the FSBL into OCM memory.

For secure boot, the PS_SRST_B input remains disabled (not enabled by CSU ROM). Secure code can enable the PS_SRST_B reset input using the CRL_APB.RESET_CTRL register.